NII Technical Report (NII-2006-001E)

Title Synthesis of Timed Circuits based on Decomposition
Authors Tomohiro Yoneda, Chris Myers
Abstract This paper presents a decomposition based method for timed circuit design that is capable of significantly reducing the cost of synthesis. In particular, this method synthesizes each output individually. It begins by contracting the timed STG to include only transitions on the output of interest and its possible trigger signals. Next, the reachable state space for this contracted STG is analyzed to determine a minimal number of additional signals which must be reintroduced into the STG to obtain CSC. The circuit for this output is then synthesized from this STG. Results show that the quality of the circuit implementation is nearly as good as the one found from the full reachable state space, but it can be applied to find circuits for which full state space methods cannot be successfully applied. The proposed method has been implemented as a part of our tool nutas(Nii-Utah Timed Asynchronous circuit Synthesis system), and its very first version is available at
Language English
Published Feb 16, 2006
Pages 16p
PDF File 06-001E.pdf

NII Technical Reports
National Institute of Informatics