Abstract |
This work proposes an efficient methodology to synthesize timed
circuits from high level specification languages. In particular, this
paper presents a systematic procedure for translating channel-level models
to time Petri net descriptions. Care is taken in this translation to guarantee
that there are no state coding violations in the resulting nets greatly
simplifying the synthesis process. This paper also presents a modular
decomposition method to break up the circuit to be synthesized such that
an efficient partial order based synthesis approach can be applied to
rapidly produce a circuit implementation. This new synthesis technique is
demonstrated by its application to the line fetch module from the TITAC2
instruction cache system. |